This invention relates to digital DLL (delay lock loop) circuits. More particularly, this invention relates to low pass filters in digital delay lock loop circuits.
Digital delay lock loop circuits typically generate a clock signal based on a periodic reference signal (e.g., from an oscillator) that maintains a specific phase relationship with that reference signal. Digital delay lock loop circuits are often used, for example, in high-speed clocked memories such as SDRAMs (synchronous dynamic random access memories).
A digital delay lock loop circuit usually includes a phase detector that detects a phase difference outside the specified phase relationship between the periodic reference signal and the periodic output signal, which is fed back to the phase detector. The phase detector provides a xe2x80x9cshiftxe2x80x9d signal, if necessary, to adjust the phase of the output signal. Such shift signals cause the delay between output signal transitions and corresponding reference signal transitions to increase or decrease as needed to reestablish the specified phase relationship.
However, phase detectors may erroneously provide shift signals in response to noise on the phase detector inputs, rather than in response to an actual phase difference between the reference signal and the output signal. This can cause errors in the output signal. For example, transient noise in a delay lock loop circuit may cause the output signal to unnecessarily shift even though the output signal is tracking the reference signal accurately. After the output signal shifts, it may no longer be within the specified phase relationship with the reference signal. This can cause logic errors in cases where, for example, the output signal is a clock signal shifted out of specification. Moreover, the transient noise is likely to disappear, resulting in the output signal shifting again. At the least, typical delay lock loop circuits can unnecessarily disturb an output signal.
A known solution is to couple a digital low pass filter to the output of the phase detector to prevent shifts caused by high frequency noise from propagating through to the output signal. However, these filters become relatively large and cumbersome as the low pass frequency is lowered, and thus, are not always practical.
In view of the foregoing, it would be desirable to provide a digital delay lock loop circuit having a versatile, compact low pass filter that reduces, if not prevents, the adverse effects of input noise.
It is an object of this invention to provide a digital delay lock loop circuit having a versatile, compact low pass filter that reduces, if not prevents, the adverse effects of input noise.
The invention provides an arbitrarily low, low pass filter for delay lock loop circuits. The filter preferably includes a thermometer register. Alternatively, the filter can include other circuitry that performs the same or equivalent function as the thermometer register (described below). Such alternative circuitry can include, for example, appropriately configured averaging circuits, appropriately configured counters or accumulators, etc.
The low pass filter is coupled to receive the outputs of a phase detector. The phase detector provides signals that indicate whether the periodic output signal leads or lags a periodic input reference signal outside a predetermined phase relationship. The low pass filter filters these phase detector signals, which may be caused by noise, and outputs shift signals as appropriate. The shift signals are fed to a variable-delay buffer that provides buffered versions of the input reference signal at selectable delay points.
In one embodiment of the invention, the low pass filter includes a thermometer register that has a most significant portion initialized to all logical ones or zeroes, and a least significant portion initialized to all logical zeroes or ones, respectively. The logical ones and zeros represent leading and lagging signals, respectively, or vice-versa. The thermometer register provides shift signals in response to having all logical ones or all logical zeroes. Based on the lead or lag signals received from the phase detector, the thermometer register shifts left or right, respectively, or vice-versa, shifting in a one or zero as appropriate. The thermometer register fills with all ones or all zeroes after a net number of shifts to the right or left, indicating that detection of a leading or lagging output signal a net number of times more than a lagging or leading output signal, respectively, has occurred. Thus, the thermometer register advantageously filters sudden and transient changes in phase difference as detected by the phase detectorxe2x80x94differences which may have been caused by noise.
The arbitrarily low, low pass aspect of the filter results from the scalability of the thermometer register to any size (i.e., number of bits). The larger the thermometer register, the lower the passing frequency allowed by the thermometer register and thus, the more likely that detected phase differences will not be caused by noise.